Performance Evaluation and Design Tradeoffs of On-Chip Interconnect Architectures

Mohmed Bakhouya (1) , Suboh Suboh (2) , Jaafar Gaber (1) , Tarek El-Ghazawi (3) , Smail Niar (4, 5)

1 SET - Laboratoire Systèmes et Transports
2 ECE - Department of Electrical and Computer Engineering [George Washington University]
3 CSE - Department of Computer Science & Engineering
4 LAMIH - Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201
5 DART - Contributions of the Data parallelism to real time

Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs. In this paper, a Network Calculusbased methodology is presented to analyze and evaluate the performance and cost metrics, such as latency and energy consumption. The 2D Mesh, Spidergong and WK-recursive on-chip interconnect architectures are analyzed using this methodology and results are compared with those produced using simulations. The values obtained by simulations and by analysis show similar trends in the same order of magnitude. Furthermore, WK outperforms the other on-chip interconnects in all considered metrics

Mots clés: Network-on-Chip; On-chip interconnect; Analytical modeling and evaluation; Design Tradeoffs; Network calculus

Domaines: Calcul parallèle, distribué et partagé [cs.DC]; Arithmétique des ordinateurs

Mohmed Bakhouya, Suboh Suboh, Jaafar Gaber, Tarek El-Ghazawi, Smail Niar. Performance Evaluation and Design Tradeoffs of On-Chip Interconnect Architectures. 2010. ⟨hal-00534521⟩