Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis system

Apostolos Kountouris (1) , Christophe Wolinski (2)

1 FT R&D - France Télécom Recherche & Développement
2 EP-ATR - Environnement de programmation d'applications temps réel

In high-level hardware synthesis (HLS), there is a gap in the quality of the synthesized results between data-flow and control-flow dominated behavioral descriptions. Heuristics destined for the former usually perform poorly on the latter. To close this gap, the CODESIS interactive HLS tool relies on a unifying intermediate design representation and adapted heuristics that are able to accommodate both types of designs, as well as designs of a mixed data-flow and control-flow nature. Preliminary experimental results in mutual exclusiveness detection and in efficiently scheduling conditional behaviors, are encouraging and prompt for more extensive experimentation.

Mots clés: flow graphs; high level synthesis; interactive systems; scheduling; CODESIS interactive high-level synthesis system; adapted heuristics; conditional behaviour scheduling; control-flow dominated behavioural descriptions; data-flow dominated behavioural descriptions; hierarchical conditional dependency graphs; high-level hardware synthesis; mutual exclusiveness detection; synthesised results quality; unifying intermediate design representation

Domaines: Systèmes embarqués

Apostolos Kountouris, Christophe Wolinski. Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis system. 13th International Symposium on System Synthesis (ISSS '00), Sep 2000, Madrid, Spain. pp.66-71, ⟨10.1109/ISSS.2000.874030⟩. ⟨hal-00545528⟩