VHDL & Signal: A Cooperative Approach
Résumé
This work presents the study done to integrate VHDL with the Signal environment for reactive systems, signal processing and real-time applications. This will be done by translating the language Signal into VHDL and conversely, VHDL into Signal. As the scope and the use of these two languages are different, a subset of both languages will be defined to correctly interface them. By allowing description in a mixture of VHDL and Signal, designers gain from the strengths of both languages and their tool environments.
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Systèmes embarqués
Origine : Fichiers produits par l'(les) auteur(s)
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