Formal Verification of Fault Tolerant NoC-based Architecture

Manamiary Bruno Andriamiarina (1, 2) , Hayat Daoud (3) , Mostefa Belarbi (3) , Dominique Méry (1) , Camel Tanougast (4)

1 MOSEL - Proof-oriented development of computer-based systems
2 VERIDIS - Modeling and Verification of Distributed Algorithms and Systems
3 LIM - Laboratoire Informatique Mathématiques
4 LIEN - Laboratoire d'Instrumentation Electronique de Nancy

Approaches to design fault tolerant Network-on-Chip (NoC) for System-on-Chip(SoC)-based reconfigurable Field-Programmable Gate Array (FPGA) technology are challenges on the conceptualisation of the Multiprocessor System-on-Chip (MPSoC) design. For this purpose, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in a validation architecture. The Event-B formal method is a promising formal approach that can be used to develop, model and prove accurately the domain of SoCs and MPSoCs. This paper gives a formal verification of a NoC architecture, using the Event-B methodology. The formalisation process is based on an incremental and validated correct-by-construction development of the NoC architecture.

Domaines: Modélisation et simulation

Manamiary Bruno Andriamiarina, Hayat Daoud, Mostefa Belarbi, Dominique Méry, Camel Tanougast. Formal Verification of Fault Tolerant NoC-based Architecture. First International Workshop on Mathematics and Computer Science (IWMCS2012), Mostefa BELARBI - University of Tiaret - Algeria, Dec 2012, Tiaret, Algeria. ⟨hal-00763092⟩