G-MPSoC: Generic Massively Parallel Architecture on FPGA

Hana Krichene (1) , Mouna Baklouti (2) , Mohamed Abid (2) , Philippe Marquet (1) , Jean-Luc Dekeyser (1)

1 DREAMPAL - Dynamic Reconfigurable Massively Parallel Architectures and Languages
2 CES Lab - Computer & Embedded Systems

Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms (filtering, correlation, etc.) and their numerous parameters. Having a flexible and pro-grammable system that adapts to changing and various characteristics of these applications reduces the design cost. In this context, we propose in this paper Generic Massively Parallel architecture (G-MPSoC). G-MPSoC is a System-on-Chip based on a grid of clusters of Hardware and Software Computation Elements with different size, performance, and complexity. It is composed of parametric IP-reused modules: processor, controller, accelerator, memory, interconnection network, etc. to build different architecture configurations. The generic structure of G-MPSoC facilitates its adaptation to the intensive signal processing applications requirements. This paper presents G-MPSoC architecture and details its different components. The FPGA-based implementation and the experimental results validate the architectural model choice and show the effectiveness of this design.

Mots clés: Generic architecture; MPP; FPGA; IP-reused; parallelism; Key–Words: SoC

Domaines: Systèmes embarqués

Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser. G-MPSoC: Generic Massively Parallel Architecture on FPGA. WSEAS Transactions on circuits and systems, 2015, 14. ⟨hal-01246675⟩