SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively parallel SoC

Hana Krichene (1, 2) , Mouna Baklouti (1) , Mohamed Abid (1) , Philippe Marquet (2) , Jean-Luc Dekeyser (2) , Samy Meftali (3)

1 CES Lab - Computer & Embedded Systems
2 DREAMPAL - Dynamic Reconfigurable Massively Parallel Architectures and Languages
3 DREAMPAL - Dynamic Reconfigurable Massively Parallel Architectures and Languages

Parallel communication plays a critical role in massively parallel systems, especially in distributed memory systems executing parallel programs on shared data. Therefore, integrating an interconnection network in these systems becomes essential to ensure data inter-nodes exchange. Choose the most effective communication structure must meet certain criteria: speed, size and power consumption. Indeed, the communication phase should be as fast as possible to avoid compromising parallel computing, using small and low power consumption modules to facilitate the interconnection network extensibility in a scalable system. To meet these criteria and based on a module reuse methodology, we chose to integrate a reconfigurable SCAC-Net interconnection network to communicate data in SCAC Massively parallel SoC. This paper presents the detailed hardware implementation and discusses the performance evaluation of the proposed reconfigurable SCAC-Net network.

Domaines: Systèmes embarqués

Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser, et al.. SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively parallel SoC. PDP 2016 - 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, Feb 2016, Héraklion, Greece. pp.759-762, ⟨10.1109/PDP.2016.94⟩. ⟨hal-01246680⟩