DiST: A Simple, Reliable and Scalable Method to Significantly Reduce Processor Architecture Simulation Time
Résumé
While architecture simulation is often treated as a methodology issue, it is at the core of most processor architecture research works,
and simulation speed is often the bottleneck of the typical trial-and-error research process. To speedup simulation during this research process and get trends faster, researchers usually reduce the
trace size. More sophisticated techniques like trace sampling or
distributed simulation are scarcely used because they are considered unreliable and complex due to their impact on accuracy and
the associated warm-up issues.
In this article, we present DiST, a practical distributed simulation scheme where, unlike in other simulation techniques that trade
accuracy for speed, the user is relieved from most accuracy issues
thanks to an automatic and dynamic mechanism for adjusting the
warm-up interval size. Moreover, the mechanism is designed so
as to always privilege accuracy over speedup. The speedup scales
with the amount of available computing resources, bringing an average 7.35 speedup on 10 machines with an average IPC error of
1.81% and a maximum IPC error of 5.06%.
Besides proposing a solution to the warm-up issues in distributed
simulation, we experimentally show that our technique is significantly more accurate than trace size reduction or trace sampling for
identical speedups. We also show that not only the error always remains small for IPC and other metrics, but that a researcher can reliably base research decisions on DiST simulation results. Finally,
we explain how the DiST tool is designed to be easily pluggable
into existing architecture simulators with very few modifications.
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