A Flexible SoC and Its Methodology for Parser-Based Applications

Bertrand Le Gal (1) , Yérom-David Bromberg (2) , Laurent Réveillère (3) , Jigar Solanki (3)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 ASAP - As Scalable As Possible: foundations of large scale dynamic distributed systems
3 LaBRI - Laboratoire Bordelais de Recherche en Informatique

Embedded systems are being increasingly network interconnected. They require to interact with their environment through text-based protocol messages. Parsing such messages is control-dominated. The work presented in this article attempts to accelerate message parsers using a codesign-based approach. We propose a generic architecture associated to an automated design methodology that enables a SoC/SoPC system generation from high-level specifications of message protocols. Experimental results obtained on a Xilinx ML605 board show acceleration factors ranging from 4 to 11. Both static and dynamic reconfigurations of coprocessors are discussed then evaluated so as to reduce the system hardware complexity.

Mots clés: Codesign; Hardware accelerators; Protocol parsers

Domaines: Système d'exploitation [cs.OS]

Bertrand Le Gal, Yérom-David Bromberg, Laurent Réveillère, Jigar Solanki. A Flexible SoC and Its Methodology for Parser-Based Applications. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2016, 10 (1), pp.4. ⟨10.1145/2939379⟩. ⟨hal-01415653⟩