Extending Intel-x86 Consistency and Persistency

Azalea Raad (1) , Luc Maranget (2) , Viktor Vafeiadis (3)

1 Department of Computing [Imperial College London]
2 CAMBIUM - Langages de programmation : systèmes de types, concurrence, preuve de programme
3 MPI-SWS - Max Planck Institute for Software Systems

Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of its available features that are relevant for the consistency semantics of multi-threaded programs as well as the persistency semantics of programs interfacing with non-volatile memory. We extend these formalisations to cover: (1) non-temporal writes, which provide higher performance and are used to ensure that updates are flushed to memory; (2) reads and writes to other Intel-x86 memory types, namely uncacheable, write-combined, and write-through; as well as (3) the interaction between these features. We develop our formal model in both operational and declarative styles, and prove that the two characterisations are equivalent. We have empirically validated our formalisation of the consistency semantics of these additional features and their subtle interactions by extensive testing on different Intel-x86 implementations.

Mots clés: Weak memory; Cacheability; Memory types; Non-temporal accesses; Intel-x86; Non-volatile memory; Memory persistency

Domaines: Langage de programmation [cs.PL]

Azalea Raad, Luc Maranget, Viktor Vafeiadis. Extending Intel-x86 Consistency and Persistency: Formalising the Semantics of Intel-x86 Memory Types and Non-Temporal Stores. POPL 2022 - Symposium on Principles of Programming Languages, Jan 2022, Philadelphia, United States. ⟨10.1145/3498683⟩. ⟨hal-03426997⟩