Multiplication-addition modulaire: algorithmes itératifs et implantations sur FPGA
Résumé
This paper describes several improvements of an iterative algorithm for modular multiplication originally proposed by Jeong and Burleson. A first modification of the recurrence relation allows us to implement a fused multiply and add unit. Then, we show how to reduce the circuit area by a factor two when the operator offers the possibility to choose the modulo among a set m_1, m_2,, m_q. A new iterative algorithm making the implementation of modular exponentiation easier is eventually discussed. For 16-bit numbers, our operators perform for instance 6 millions of operations per second on a Virtex-E device while only requiring 17 slices.