A compact Multi-Chip-Module Implementation of a Multi-Precision Neural Network Classifier - INRIA - Institut National de Recherche en Informatique et en Automatique Accéder directement au contenu
Communication Dans Un Congrès Année : 2001

A compact Multi-Chip-Module Implementation of a Multi-Precision Neural Network Classifier

Amine Bermak
  • Fonction : Auteur
Dominique Martinez

Résumé

This paper describes a novel Multi-Chip Module (MCM) digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 $\mu$m technology.

Domaines

Autre [cs.OH]
Fichier non déposé

Dates et versions

inria-00108072 , version 1 (19-10-2006)

Identifiants

  • HAL Id : inria-00108072 , version 1

Citer

Amine Bermak, Dominique Martinez. A compact Multi-Chip-Module Implementation of a Multi-Precision Neural Network Classifier. IEEE International Symposium on Circuits and Systems - ISCAS'2001, May 2001, Sydney, Australia, pp.249-252. ⟨inria-00108072⟩
101 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More