Verification of clock constraints: CCSL Observers in Esterel

Charles André (1)

1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints

The Clock Constraint Specification Language (CCSL) has been informally introduced in the specifications of the UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE). In a previous report entitled ``Syntax and Semantics of the Clock Constraint Specification Language'', we equipped a kernel of CCSL with an operational semantics. In the present report we pursue this clarification effort by giving a mathematical characterization to each CCSL constructs. We also propose a systematic approach to the formal verification of CCSL constraints with dedicated Observers. A comprehensive library of Esterel modules, which supports this approach, is provided.

Mots clés: CCSL; UML; time constraints; verification; observer; Esterel

Domaines: Systèmes embarqués

Charles André. Verification of clock constraints: CCSL Observers in Esterel. [Research Report] RR-7211, INRIA. 2010, pp.59. ⟨inria-00458847⟩