Integrating Hardware Limitations in CAN Schedulability Analysis - INRIA - Institut National de Recherche en Informatique et en Automatique Accéder directement au contenu
Communication Dans Un Congrès Année : 2010

Integrating Hardware Limitations in CAN Schedulability Analysis

Dawood Khan
  • Fonction : Auteur
  • PersonId : 865102
Reinder Bril
  • Fonction : Auteur
  • PersonId : 864764
Nicolas Navet
  • Fonction : Auteur
  • PersonId : 830599

Résumé

The existing schedulability analysis for the Controller Area Network (CAN) does not take into account that a CAN controller has finite buffer space to store outgoing messages and high priority messages may suffer from priority inversion if the buffers are already occupied by low priority messages. This gives rise to an additional delay for high priority messages, which, if not considered, may result in a deadline violation. In this paper, we explain the cause of this additional delay and extend the existing CAN schedulability analysis to integrate it. Finally,we suggest implementation guidelines that minimizes both the run-time CPU overhead and the additional delay due to priority inversion.
Fichier principal
Vignette du fichier
PID1248001.pdf (121.54 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

inria-00542635 , version 1 (03-12-2010)

Identifiants

  • HAL Id : inria-00542635 , version 1

Citer

Dawood Khan, Reinder Bril, Nicolas Navet. Integrating Hardware Limitations in CAN Schedulability Analysis. 8th International Workshop on Factory Communication Systems, May 2010, Nancy, France. ⟨inria-00542635⟩
79 Consultations
236 Téléchargements

Partager

Gmail Facebook X LinkedIn More