Evaluation of VLSI Layout Implementation for Efficiency

Michel Robert (1) , Joel Trauchessec (2) , Guy Cathébras (3, 1) , Vincent Bonzom (2) , Nadine Azemard (1) , Denis Deschacht (1) , Daniel Auvergne (2)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 DEMAR - Artificial movement and gait restoration

As an attempt to define a priori mapping rules for performance driven layout, the authors show in this paper how an automatic module generator can be used to compare different implementation styles of regular layout. Speed and area performances of gate and linear matrix approaches are compared. It is clearly shown that abutment of diffusions results in lower 'locox' parasitic capacitances inducing higher speed performances for linear matrix style.

Mots clés: CMOS logic circuits

Domaines: Modélisation et simulation; Micro et nanotechnologies/Microélectronique

Michel Robert, Joel Trauchessec, Guy Cathébras, Vincent Bonzom, Nadine Azemard, et al.. Evaluation of VLSI Layout Implementation for Efficiency. EURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩. ⟨lirmm-00239384⟩