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inria-00416502v1  Conference papers
Mathieu FavergePierre Ramet. A NUMA Aware Scheduler for a Parallel Sparse Direct Solver
Workshop on Massively Multiprocessor and Multicore Computers, INRIA, Feb 2009, Rocquencourt, France. 5p
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hal-00547413v1  Journal articles
Remi AbgrallPierre RametRobin Huart. Numerical simulation of unsteady MHD flows and applications
Magnetohydrodynamics c/c of Magnitnaia Gidrodinamika, Institute of Physics, University of Latvia, 2009, 45 (2), pp.225-232
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hal-00924977v1  Conference papers
Casadei AstridLuc GiraudPierre RametJean Roman. Towards Domain Decomposition with Balanced Halo
Workshop Celebrating 40 Years of Nested Dissection, Jul 2013, Waterloo, Canada
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hal-00924979v1  Conference papers
Pierre Ramet. From hybrid architectures to hybrid solvers
Workshop Celebrating 40 Years of Nested Dissection, Jul 2013, Waterloo, Canada
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hal-00924989v2  Conference papers
Salli MoustafaIvan Dutka MalenLaurent PlagneAngélique PonçotPierre Ramet. Shared Memory Parallelism for 3D Cartesian Discrete Ordinates Solver
Joint International Conference on Supercomputing in Nuclear Applications and Monte Carlo 2013, Oct 2013, Paris, France
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hal-00987099v1  Conference papers
Casadei AstridPierre RametJean Roman. Nested dissection with balanced halo
Sixth SIAM Workshop on Combinatorial Scientific Computing, Jul 2014, Lyon, France
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hal-01078364v1  Conference papers
Salli MoustafaMathieu FavergeLaurent PlagnePierre Ramet. Parallel 3D Sweep Kernel with PARSEC
HPCC Workshop on HPC-CFD in Energy/Transport Domains, Aug 2014, Paris, France
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hal-01078362v1  Conference papers
Salli MoustafaMathieu FavergeLaurent PlagnePierre Ramet. 3D Cartesian Transport Sweep for Massively Parallel Architectures with PARSEC
IEEE International Parallel & Distributed Processing Symposium (IPDPS 2015), May 2015, Hyderabad, India. pp.581-590, ⟨10.1109/IPDPS.2015.75⟩
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hal-01100962v1  Conference papers
Casadei AstridPierre RametJean Roman. An improved recursive graph bipartitioning algorithm for well balanced domain decomposition
IEEE International Conference on High Performance Computing (HiPC 2014), Dec 2014, Goa, India. pp.1-10, ⟨10.1109/HiPC.2014.7116878⟩
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hal-01142204v1  Reports
Maher AlayaMathieu FavergeXavier LacosteAlexandre Péré-LaperneJacques Péré-Laperne et al.  Simul'Elec and PASTIX interface specifications
[Rapport Technique] RT-0458, INRIA Bordeaux; AlgoTech; INRIA. 2015
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hal-01276746v2  Reports
Grégoire PichonMathieu FavergePierre RametJean Roman. Reordering strategy for blocking optimization in sparse linear solvers
[Research Report] RR-8860, Inria Bordeaux Sud-Ouest; LaBRI - Laboratoire Bordelais de Recherche en Informatique; Bordeaux INP; Université de Bordeaux. 2016, pp.26
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hal-01450732v3  Reports
Grégoire PichonEric DarveMathieu FavergePierre RametJean Roman. Sparse Supernodal Solver Using Block Low-Rank Compression
[Research Report] RR-9022, Inria Bordeaux Sud-Ouest. 2017, pp.24
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hal-01485507v2  Journal articles
Grégoire PichonMathieu FavergePierre RametJean Roman. Reordering Strategy for Blocking Optimization in Sparse Linear Solvers
SIAM Journal on Matrix Analysis and Applications, Society for Industrial and Applied Mathematics, 2017, SIAM Journal on Matrix Analysis and Applications, 38 (1), pp.226 - 248. ⟨10.1137/16M1062454⟩
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hal-01502215v1  Conference papers
Grégoire PichonEric DarveMathieu FavergePierre RametJean Roman. Sparse Supernodal Solver Using Block Low-Rank Compression
18th IEEE International Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC 2017), Jun 2017, Orlando, United States