High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology

Philippe Renaud (1) , Amaury Gendron (1) , Marise Bafleur (2) , Nicolas Nolhier (2)

1 Freescale Semiconducteurs
2 LAAS - Laboratoire d'analyse et d'architecture des systèmes

A new device dedicated to the ESD protection of high voltage I/Os is presented. In addition to the use of specific design guidelines, the concept consists in coupling an open-base lateral PNP with a vertical avalanche diode within the same structure to obtain a non-snapback behavior together with very good RON capabilities (~1Ω). The protection of high voltage I/Os with a narrow ESD design window ranging from 80V to 100V can be implemented in a reduced surface of 151*140 μm2, which represents a state-of-the-art breakthrough.

Mots clés: ESD protection; High voltage I/Os; smart power technology; PNP bipolar transistor

Domaines: Micro et nanotechnologies/Microélectronique

Philippe Renaud, Amaury Gendron, Marise Bafleur, Nicolas Nolhier. High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Oct 2007, BOSTON, United States. pp.359. ⟨hal-00195362⟩