Design Techniques and Modeling for 60GHz Applications With a 65nm-CMOS-RF Technology

Sofiane Aloui (1) , Eric Kerherve (1) , Robert Plana (2) , Didier Belot (3)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 LAAS - Laboratoire d'analyse et d'architecture des systèmes
3 ST-CROLLES - STMicroelectronics [Crolles]

To exploit the unlicensed band at frequencies around 60GHz, a certain number of design rules is considered. This paper highlights the difficulties to design a millimeter CMOS power amplifier (PA). A model of a compact inductor and interconnect lines is detailed. This model takes into account substrate and resistive parasitic. A 65nm CMOS technology from STMicroelectronics has been used. Innovative techniques are implemented in the design of a power amplifier (PA) which is optimized to deliver the maximum linear output power. To obtain good performances in a small surface of silicon, it has been designed, with both lumped and distributed elements. The PA delivers a linear output power of 8.9dBm with just an area of 0.48mm*0.6mm including pads

Mots clés: Design Techniques; 60GHz; 65nm-CMOS-RF

Domaines: Micro et nanotechnologies/Microélectronique

Sofiane Aloui, Eric Kerherve, Robert Plana, Didier Belot. Design Techniques and Modeling for 60GHz Applications With a 65nm-CMOS-RF Technology. Global Symposium on Millimeter Waves, 2008. GSMM, Apr 2008, Nanjing, China. pp.241-244. ⟨hal-00326848⟩