Design Guidelines to Achieve a Very High ESD Robustness in a Self-Biased NPN

David Trémouilles (1) , Géraldine Bertrand (2) , Marise Bafleur (1) , Nicolas Nolhier (1) , Lionel Lescouzères (2)

1 LAAS - Laboratoire d'analyse et d'architecture des systèmes
2 ON Semiconductor

In this paper, using extensive TCAD simulations and measurement results, we analyze the basic mechanisms involved during an ESD stress in a self-biased NPN bipolar transistor used as an ESD protection. From the deep understanding of these mechanisms, we define design guidelines to achieve a very high ESD robustness (=10kV) in this type of device. These guidelines are validated on several CMOS technologies.

Mots clés: ESD; self-biased NPN; current focalization; moving hot spot

Domaines: Micro et nanotechnologies/Microélectronique

David Trémouilles, Géraldine Bertrand, Marise Bafleur, Nicolas Nolhier, Lionel Lescouzères. Design Guidelines to Achieve a Very High ESD Robustness in a Self-Biased NPN. Electrical Overstress and Electrostatic Discharge Symposium, Oct 2002, Charlotte, United States. pp.281-288. ⟨hal-00383352⟩