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IC immunity modeling process validation using on-chip measurements

Abstract : Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process.
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Submitted on : Monday, February 3, 2014 - 9:44:34 AM
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Sonia Ben Dhia, Alexandre Boyer, Bertrand Vrignon, Mikael Deobarro. IC immunity modeling process validation using on-chip measurements. Journal of Electronic Testing, Springer Verlag, 2012, 28 (3), pp.339-348. ⟨10.1007/s10836-012-5294-3⟩. ⟨hal-00936080⟩



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