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Journal articles
IC immunity modeling process validation using on-chip measurements
Abstract : Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process.
Cited literature [10 references]
https://hal.archives-ouvertes.fr/hal-00936080
Contributor : Alexandre Boyer <>
Submitted on : Monday, February 3, 2014 - 9:44:34 AM
Last modification on : Friday, January 10, 2020 - 9:10:14 PM
Long-term archiving on: : Saturday, May 3, 2014 - 10:55:11 PM
Contributor : Alexandre Boyer <>
Submitted on : Monday, February 3, 2014 - 9:44:34 AM
Last modification on : Friday, January 10, 2020 - 9:10:14 PM
Long-term archiving on: : Saturday, May 3, 2014 - 10:55:11 PM
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