IC immunity modeling process validation using on-chip measurements

Sonia Ben Dhia (1) , Alexandre Boyer (1) , Bertrand Vrignon (2) , Mikael Deobarro (3)

1 LAAS-ESE - Équipe Énergie et Systèmes Embarqués
2 Freescale Semiconductor
3 LATTIS - Laboratoire Toulousain de Technologie et d'Ingénierie des Systèmes

Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process.

Mots clés: Integrated circuit; on-chip measurement; immunity modelling; power supply network modelling

Domaines: Electronique

Sonia Ben Dhia, Alexandre Boyer, Bertrand Vrignon, Mikael Deobarro. IC immunity modeling process validation using on-chip measurements. Journal of Electronic Testing: : Theory and Applications, 2012, 28 (3), pp.339-348. ⟨10.1007/s10836-012-5294-3⟩. ⟨hal-00936080⟩