Analysis and optimization of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

Ignasi Cortés (1) , Gaëtan Toulon (2) , Frédéric Morancho (3) , David Flores (1) , Elsa Hugonnard-Bruyère (4) , Bruno Villard (4)

1 CNM - Centro Nacional de Microelectronica [Spain]
2 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie
3 LAAS - Laboratoire d'analyse et d'architecture des systèmes
4 ATMEL [Rousset]

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Mots clés: Thin-SOI technology; CMOS; LDMOS; RESURF; P-channel; NBL; TCAD

Domaines: Electronique

Ignasi Cortés, Gaëtan Toulon, Frédéric Morancho, David Flores, Elsa Hugonnard-Bruyère, et al.. Analysis and optimization of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region. Solid-State Electronics, 2012, 70, pp.8-13. ⟨10.1016/j.sse.2011.11.012⟩. ⟨hal-01054152⟩