EMC performance analysis of a Processor/Memory System using PCB and Package-On-Package

Etienne Sicard (1) , Alexandre Boyer (2) , Priscillia Fernandez-Lopez (3) , An Zhou (3) , Nicolas Marier (3) , Frédéric Lafon (3)

1 INSA Toulouse - Institut National des Sciences Appliquées - Toulouse
2 LAAS-ESE - Équipe Énergie et Systèmes Embarqués
3 VALEO

In this paper, the signal integrity (SI) and Electromagnetic Compatibility (EMC) performance of System-On-Chip (SoC) and stacked memory using Package-On-Package (PoP) technology is investigated. The reconfiguration of the IC-EMC software platform to PoP is described. From an existing 2D assembly using a discrete 65-nm SoC product, the benefits of PoP integration using a next-generation 28-nm product with stacked memory are analyzed, based on simulation and predictive analysis performed using IC-EMC software platform.

Mots clés: Microcontroller and memory; PoP; Equivalent bus model; Near-Field Scan; IBIS; Signal integrity; EMC

Domaines: Electronique

Etienne Sicard, Alexandre Boyer, Priscillia Fernandez-Lopez, An Zhou, Nicolas Marier, et al.. EMC performance analysis of a Processor/Memory System using PCB and Package-On-Package. 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2015), Nov 2015, Edimburgh, United Kingdom. 6p. ⟨hal-01225364⟩