A Multi-Core Interference-Aware Schedulability Test for IMA Systems, as a Guide for SW/HW Integration

Soukayna M'Sirdi (1, 2) , Wenceslas Godard (1) , Marc Pantel (3, 4)

1 Airbus Group Innovations
2 IRIT - Institut de recherche en informatique de Toulouse
3 IRIT-ACADIE - Assistance à la Certification d’Applications DIstribuées et Embarquées
4 Toulouse INP - Institut National Polytechnique (Toulouse)

In this paper we propose a framework for the automated integration and timing analysis of IMA (Integrated Modular Avionics) applications on multi-core environments. To do so, we present a derivation of the response time analysis formulation by Kim et al. in [12] that takes into account inter-task interference due to sharing the access to the main memory. We adapt the work in [12] to propose a sufficient schedulability test that is adapted both to IMA systems and heterogeneous multi-core platforms. We then exploit this test to guide the design space exploration during the SW/HW integration phase, to select a partition-to-core allocation so that all deadlines are met despite the existence of hardware interference.

Mots clés: multi-core; memory interference; allocation; IMA applications; scheduling analysis; formal methods

Domaines: Systèmes embarqués

Soukayna M'Sirdi, Wenceslas Godard, Marc Pantel. A Multi-Core Interference-Aware Schedulability Test for IMA Systems, as a Guide for SW/HW Integration. 8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), Jan 2016, TOULOUSE, France. ⟨hal-01289687⟩