A new methodology to build the Internal Activity Block of ICEM-CE for complex Integrated Circuits

Chaimae Ghfiri (1) , Alexandre Boyer (2) , André Durier (1) , Sonia Ben Dhia (2)

1 IRT Saint Exupéry - Institut de Recherche Technologique
2 LAAS-ESE - Équipe Énergie et Systèmes Embarqués

End-users of integrated circuits need models to anticipate and solve conducted emission issues at board level in a short time. The standard IEC62433-2 ICEM-CE has been proposed to respond to this demand. Although the standard proposes methods to extract circuit models from measurements, they cannot provide activity dependent models and may lead to inaccurate results for large and complex circuits. This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model adapted to large digital integrated circuits and validated on a FPGA. The method is based on a predictive approach using the estimation tools of the dynamic power and the data path delays proposed by the manufacturer of the integrated circuit.

Mots clés: Integrated circuits; ICEM-CE standard; FPGA; Model; conducted emission; modeling; internal activity

Domaines: Electronique; Performance et fiabilité [cs.PF]

Chaimae Ghfiri, Alexandre Boyer, André Durier, Sonia Ben Dhia. A new methodology to build the Internal Activity Block of ICEM-CE for complex Integrated Circuits. IEEE Transactions on Electromagnetic Compatibility, 2018, 60 (5), pp.1500-1509. ⟨10.1109/TEMC.2017.2767084⟩. ⟨hal-01659770⟩