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1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors

Abstract : Low-frequency noise characteristics have been investigated in arrays of 14 nm gate-all-around vertical silicon junction-less nanowire transistors. Extensive measurements have been performed to study the evolution of the 1/f noise as a function of bias for nanowire arrays with different nanowire diameters and several numbers of nanowires in parallel. Measured drain current noise can be explained well by correlated mobility fluctuation noise theory. Although the conduction is mainly limited by the bulk, i.e., the core of the nanowire, additional trapping/release of charge carriers is observed due to an accumulation channel formed at higher gate bias. Additionally, for the first time in junction-less transistors, evidence of significant noise contribution from access regions at higher bias is observed that provides insight into 1/f noise origin.
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https://hal.archives-ouvertes.fr/hal-01695259
Contributor : Sebastien Fregonese <>
Submitted on : Monday, January 29, 2018 - 10:53:38 AM
Last modification on : Tuesday, September 1, 2020 - 2:44:23 PM

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Chhandak Mukherjee, Cristell Maneux, Julien Pezard, Guilhem Larrieu. 1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors. 47th IEEE ESSDERC, Sep 2017, Leuven, Belgium. ⟨10.1109/ESSDERC.2017.8066585⟩. ⟨hal-01695259⟩

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