Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs

Rémy Berthelon (1) , F. Andrieu (2) , E. Josse (1) , R. Bingert (1) , O. Weber (2) , E. Serret (1) , A. Aurand (1) , S. Delmedico (1) , V. Farys (1) , C. Bernicot (1) , E. Bechet (1) , E. Bernard (1) , T. Poiroux (2) , D. Rideau (1) , P. Scheer (1) , E. Baylac (1) , P. Perreau (2) , M.A. Jaud (2) , J. Lacord (2) , E. Petitprez (1) , A. Pofelski (1) , S. Ortolland (1) , P. Sardin (1) , D. Dutartre , Alain Claverie (3) , M. Vinet (2) , J.C. Marin (1) , M. Haond (1)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 CEMES-MEM - Matériaux et dispositifs pour l'Electronique et le Magnétisme

We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core. © 2016 IEEE.

Mots clés: CMOS integrated circuits; Integrated circuit design; Integrated circuit layout; Integrated circuit testing; VLSI circuits; CMOS technology; Co-optimization; Delay improvements; Fully depleted silicon-on-insulator; Longitudinal stress; Nanobeam diffraction; Ring oscillator; Stress management; Silicon on insulator technology

Domaines: Physique [physics]

Rémy Berthelon, F. Andrieu, E. Josse, R. Bingert, O. Weber, et al.. Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs. VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573425⟩. ⟨hal-01719493⟩