Sub-15nm gate-all-around field effect transistors on vertical silicon nanowires

Guilhem Larrieu (1) , Youssouf Guerfi (1) , X.L. Han (2) , N. Clément (2)

1 LAAS-MPN - Équipe Matériaux et Procédés pour la Nanoélectronique
2 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520

A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.

Domaines: Sciences de l'ingénieur [physics]; Micro et nanotechnologies/Microélectronique

Guilhem Larrieu, Youssouf Guerfi, X.L. Han, N. Clément. Sub-15nm gate-all-around field effect transistors on vertical silicon nanowires. Solid-State Electronics, 2017, 130, pp.9 - 14. ⟨10.1016/j.sse.2016.12.008⟩. ⟨hal-01898405⟩