On-chip sampling in CMOS integrated circuits

Sonia Ben Dhia (1) , S. Delmas-Bendhia , Fabrice Caignet , E. Sicard (2) , M. Roca

1 LAAS - Laboratoire d'analyse et d'architecture des systèmes
2 INSA Toulouse - Institut National des Sciences Appliquées - Toulouse

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-/spl mu/m CMOS technology exhibit a 100% delay increase in a long coupled line configuration.

Domaines: Sciences de l'ingénieur [physics]; Micro et nanotechnologies/Microélectronique

Sonia Ben Dhia, S. Delmas-Bendhia, Fabrice Caignet, E. Sicard, M. Roca. On-chip sampling in CMOS integrated circuits. IEEE Transactions on Electromagnetic Compatibility, 1999, 41 (4), pp.403-406. ⟨10.1109/15.809837⟩. ⟨hal-02523721⟩