Modular Multilevel SOI-CMOS Active Gate Driver Architecture for SiC MOSFETs

Nicolas C. Rouger (1) , Yazan Barazi (2, 3) , Marc Cousineau (1) , Frédéric Richardeau (1)

1 LAPLACE-CS - Convertisseurs Statiques
2 LAPLACE - LAboratoire PLasma et Conversion d'Energie
3 IRT Saint Exupéry - Institut de Recherche Technologique

High Voltage SiC power MOSFETs have specific driving challenges such as a reduced short circuit capability (compared to Si IGBTs) and a weak field oxide layer, a large gate to source driving voltage (compared to GaN FETs), a high electric field under negative gate bias in off-state and a high switching speed. The negative bias in off-state creates a high stress which reduces the reliability of the SiC MOSFET. The high positive gate bias can generate large drain saturation current in case of short circuit events. We propose a modular multilevel architecture, which takes benefits of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and to improve their reliability using an active and dynamic multilevel-selection on the switching sequences and on/off states.

Mots clés: active gate driver; multi-level; SiC gate drivers; SOI CMOS

Domaines: Micro et nanotechnologies/Microélectronique; Energie électrique

Nicolas C. Rouger, Yazan Barazi, Marc Cousineau, Frédéric Richardeau. Modular Multilevel SOI-CMOS Active Gate Driver Architecture for SiC MOSFETs. 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Sep 2020, Vienna (virtual ), Austria. pp.278-281, ⟨10.1109/ISPSD46842.2020.9170181⟩. ⟨hal-02920129⟩