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hal-01153717v1  Journal articles
Zhi-Bin YangKai HuYong-Wang ZhaoDian-Fu MaJean-Paul Bodeveix. Verification of AADL Models with Timed Abstract State Machines
Journal of Software, Science in China Press, 2015, vol. 26 (n° 2), pp. 202-222
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hal-01153777v1  Journal articles
Kai HuTeng ZhangZhi-Bin YangWai-Tek Tsai. Simulation of real-time systems with clock calculus
Simulation Modelling Practice and Theory, Elsevier, 2015, vol. 51, pp. 69-86. ⟨10.1016/j.simpat.2014.10.010⟩
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hal-01298793v1  Journal articles
Zhibin YangJean-Paul BodeveixMamoun FilaliKai HuYongwang Zhao et al.  Towards a verified compiler prototype for the synchronous language SIGNAL
Frontiers of Computer Science, Springer Verlag, 2016, vol. 10 (n° 1), pp. 37-53. ⟨10.1007/s11704-015-4364-y⟩
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hal-01285662v1  Journal articles
Kai HuTeng ZhangZhibin YangWei-Tek Tsai. Exploring AADL verification tool through model transformation
Journal of Systems Architecture, Elsevier, 2015, 61 (3-4), pp.141-156. ⟨10.1016/j.sysarc.2015.02.003⟩