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	hal-02732902v1 Preprints, Working Papers, ... Ian O'Connor, Zlatan Stanojevic, Oskar Baumgartner, Mukherjee Chhandak, Guilhem Larrieu et al. Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications 2020
	hal-01695259v1 Conference papers Mukherjee Chhandak, Cristell Maneux, Julien Pezard, Guilhem Larrieu. 1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors 47th IEEE ESSDERC, Sep 2017, Leuven, Belgium. ⟨10.1109/ESSDERC.2017.8066585⟩
	hal-02869216v1 Conference papers Mukherjee Chhandak, Guilhem Larrieu, Cristell Maneux. Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors EuroSOI-ULIS 2020, Sep 2020, Caen, France
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