Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology

Maxime Rousseau (1) , Olivier Rozeau (2) , Gérald Cibrario (2) , Gilles Le Carval (3) , Marie-Anne Jaud (3) , Patrick Leduc (4) , Alexis Farcy (5) , Antoine Marty (1)

1 LAAS-N2IS - Équipe Nano Ingénierie et Intégration des Systèmes
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 LSCDP - Laboratoire Simulation et Caractéristisation Dispositifs et Procédés
4 LTPI - Laboratoire des Technologies de Packaging et d'Intégration composants
5 ST-CROLLES - STMicroelectronics [Crolles]

Two parallel methods of simulation have been developed in order to evaluate the electrostatic impact that a through-silicon via (TSV) may have on a 65 nm MOS transistor. The first model is based on the finite element method (FEM) and the second one is related to electric component models (SPICE language). Both approaches are then compared and discussed. The SPICE model has been calibrated on the numerical one, so that it can be used for more complex devices - here, an inverter - and more systematic investigations. A range of 3D-compatible design rules have been defined. By integrating these new data on a complete 3D design methodology, we are able to design and layout simple logic circuitries based on a 2-stratum 3D architecture.

Mots clés: layout; through silicon via; 3D integration; parasitic coupling; electrostatic compatibility; design methodology; layout.

Domaines: Micro et nanotechnologies/Microélectronique

Maxime Rousseau, Olivier Rozeau, Gérald Cibrario, Gilles Le Carval, Marie-Anne Jaud, et al.. Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology. IMAPS Device Packaging Conference, Mar 2008, Phoenix, AZ, United States. pp.Session WA1: wafer-level 3D integration and through-silicon vias (TSVs) - II. ⟨hal-00273766⟩