Smart solutions for efficient dual strain integration for future FDSOI generations

A. Bonnevialle (1) , C. Le Royer (2) , Y. Morand (1) , S. Reboh (2) , C. Plantier (2) , N. Rambal (2) , J.-P. Pedini (1) , S. Kerdiles (2) , P. Besson (2) , J.-M. Hartmann (2) , D. Marseilhan (2) , B. Mathieu (2) , Rémy Berthelon (2, 1) , M. Cassé (2) , F. Andrieu (2) , D. Rouchon (2) , O. Weber (2) , F. Boeuf (1) , M. Haond (1) , Alain Claverie (3) , M. Vinet (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 CEMES-MEM - Matériaux et dispositifs pour l'Electronique et le Magnétisme

We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. 'STRASS' and 'BOX creep' techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-The-Art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: The electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles. © 2016 IEEE.

Mots clés: Creep; Hole mobility; Active regions; Creep process; Electrical data; Mobility model; Smart solutions; State of the art; Stress profile; VLSI circuits

Domaines: Physique [physics]

A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, C. Plantier, et al.. Smart solutions for efficient dual strain integration for future FDSOI generations. VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573406⟩. ⟨hal-01719489⟩